M55800A Atmel Corporation, M55800A Datasheet - Page 75

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.3.1
ARM DDI 0029G
Nonsequential cycles
Bus cycle types are encoded on the nMREQ and SEQ signals as listed in Table 3-1.
A memory controller for the ARM7TDMI processor must commit to a memory access
only on an N-cycle or an S-cycle.
A nonsequential cycle is the simplest form of bus cycle, and occurs when the processor
requests a transfer to or from an address that is unrelated to the address used in the
preceding cycle. The memory controller must initiate a memory access to satisfy this
request.
The address class and (nMREQ and SEQ) signals that comprise an N-cycle are
broadcast on the bus. At the end of the next bus cycle the data is transferred between the
CPU and the memory. It is not uncommon for a memory system to require a longer
access time (extending the clock cycle) for nonsequential accesses. This is to allow time
for full address decoding or to latch both a row and column address into DRAM. This
is illustrated in Figure 3-2 on page 3-6.
In Figure 3-2 on page 3-6, nMREQ and SEQ are highlighted where they are valid to
indicate the N-cycle.
Note
Copyright © 1994-2001. All rights reserved.
nMREQ
0
0
1
1
SEQ
0
1
0
1
Bus cycle type
N-cycle
S-cycle
I-cycle
C-cycle
Description
Nonsequential cycle
Sequential cycle
Internal cycle
Coprocessor register transfer cycle
Table 3-1 Bus cycle types
Memory Interface
3-5