M55800A Atmel Corporation, M55800A Datasheet - Page 161
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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6.12
ARM DDI 0029G
Cycle
1
2
3
Software interrupt and exception entry
Address
pc+2L
Xn
Xn+4
Xn+8
Exceptions (including software interrupts) force the PC to a particular value and cause
the instruction pipeline to be refilled. During the first cycle the forced address is
constructed, and a mode change can take place. The return address is moved to R14 and
the CPSR to SPSR_svc.
During the second cycle the return address is modified to facilitate return, though this
modification is less useful than in the case of the branch with link instruction.
The third cycle is required only to complete the refilling of the instruction pipeline.
The cycle timings are listed in Table 6-15 where:
•
•
•
•
MAS
[1:0]
i
2
2
pc for:
—
—
—
—
C represents the current mode-dependent value
T represents the current state-dependent value
Xn is the appropriate trap address.
nRW
0
0
0
Copyright © 1994-2001. All rights reserved.
software interrupts is the address of the SWI instruction
Prefetch Aborts is the address of the aborting instruction
Data Aborts is the address of the instruction following the one which
attempted the aborted data transfer
other exceptions is the address of the instruction following the last one to
be executed before entering the exception
Data
(pc+2L)
(Xn)
(Xn+4)
Table 6-15 Software Interrupt instruction cycle operations
nMREQ
0
0
0
SEQ
0
1
1
nOPC
0
0
0
nTRANS
C
1
1
Instruction Cycle Timings
Mode
old
exception
exception
T
0
0
TBIT
6-19
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