M42800A Atmel Corporation, M42800A Datasheet - Page 213

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 24-4. Description of the Number of Standard Wait States
24.2
24.3
24.4
24.5
1779D–ATARM–14-Apr-06
Possible Glitches on MCKO while Commuting Clock
Initializing SPI in Master Mode May Cause Problems
Break is Sent before Last Written Character
End of Break is not Guaranteed
MCKI
NWAIT
NCS
NWE
Access Length = One Wait State + Assertion of the NWAIT for One More Cycle
Unpredictable transitional pulses may occur on the MCKO pin when modifying the MCKOSS
field in the PMC Clock Generator Mode Register. The length of these glitches can be lower
than the lowest period of the selected or current clock. When switching from the Slow Clock
(i.e., after reset) to any of the PLL outputs (inverted or divided by 2), a pulse of less than 10 ns
is output on the pin MCKO.
The glitch description above is merely a user warning/possibility. If the glitches do occur, there
is no Problem Fix/Workaround to propose.
Initializing the SPI in master mode may cause a mode fault detection.
In order to prevent this error, the user should pull up the PA14/NPCSA0/NSSA pin for SPIA or
the PA21/NPCSA0/NSSB pin for SPIB to the V
When the Start Break command is activated in the USART Control Register and while a char-
acter is in the USART Transmit Holding Register, the break is transmitted before the
character.
The user must wait for the TXEMPTY flag in the USART Status Register before sending a
break command.
When performing a Stop Break command, the USART transmitter normally inserts a “12-bit at
level 1” sequence after the break. This feature is not guaranteed.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
EB16
DDIO
power supply.
Erroneous NWE Rising
AT91M42800A
213