M42800A Atmel Corporation, M42800A Datasheet - Page 122

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

17.1
Each USART channel has the following external signals:
17.2
122
Name
SCK
RXD
TXD
Pin Description
Baud Rate Generator
AT91M42800A
Description
USART Serial clock can be configured as input or output:
SCK is configured as input if an External clock is selected (USCLKS = 3)
SCK is driven as output if the External Clock is disabled (USCLKS
Transmit Serial Data is an output
Receive Serial Data is an input
Notes:
The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the
Receiver and the Transmitter.
The Baud Rate Generator can select between external and internal clock sources. The exter-
nal clock source is SCK. The internal clock sources can be either the master clock MCK or the
master clock divided by 8 (MCK/8).
Note:
When the USART is programmed to operate in Asynchronous Mode (SYNC = 0 in the Mode
Register US_MR), the selected clock is divided by 16 times the value (CD) written in
US_BRGR (Baud Rate Generator Register). If US_BRGR is set to 0, the Baud Rate Clock is
disabled.
When the USART is programmed to operate in Synchronous Mode (SYNC = 1) and the
selected clock is internal (USCLKS
the internal selected clock divided by the value written in US_BRGR. If US_BRGR is set to 0,
the Baud Rate Clock is disabled.
In Synchronous Mode with external clock selected (USCLKS = 3), the clock is provided
directly by the signal on the SCK pin. No division is active. The value written in US_BRGR has
no effect.
1. After a hardware reset, the USART clock is disabled by default (see
2. After a hardware reset, the USART pins are deselected by default (see
In all cases, if an external clock is used, the duration of each of its levels must be longer than the
system clock (MCK) period. The external clock frequency must be at least 2.5 times lower than
the system clock.
ment Controller” on page
before any access to the User Interface of the USART.
Controller” on page
transmitter or receiver. If the user selects one of the internal clocks, SCK can be configured
as a PIO.
Baud Rate
97). The user must configure the PIO Controller before enabling the
Baud Rate
55). The user must configure the Power Management Controller
3 in the Mode Register US_MR), the Baud Rate Clock is
=
=
Selected Clock
3) and Clock output is enabled (CLKO = 1)
Selected Clock
16 x CD
CD
”PMC: Power Manage-
1779D–ATARM–14-Apr-06
”PIO: Parallel I/O