ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 50

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28. LCD - Liquid Crystal Display Controller
28.1
28.2
8074A–AVR–10/11
Features
Overview
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The LCD controller is intended for monochrome passive liquid crystal display (LCD) with up to 4
Common terminals and up to 25 segments terminals. If the application does not need all the
LCD segments available on the XMEGA, up to 16 of the unused LCD pins can be used as gen-
eral purpose I/O pins.
The LCD controller can be clocked by an internal or an external asynchronous 32kHz clock
source. This 32kHz oscillator source selection is the same as for the real time counter (RTC).
Dedicated Low Power Waveform, Contrast Control, Extended Interrupt Mode, Selectable Frame
Frequency and Blink functionality are supported to offload the CPU, reduce interrupts and
reduce power consumption.
To reduce hardware design complexity, the LCD includes integrated LCD buffers, an integrated
power supply voltage and an innovative SWAP mode. Using SWAP mode, the hardware design-
ers have more flexibility during board layout as they can rearrange the pin sequence on
Segment and/or Common Terminal Buses.
Figure 28-1. LCD overview
Display capacity up to 25 segments and up to 4 common terminals
Supports up to 16 GPIO's
Shadow display memory gives full freedom in segment update
ASCII character mapping
Swap capability option on segment and/or common terminal buses
Supports from static up to 1/4 duty
Supports static and 1/3 bias
LCD driver active in power save mode for low power operation
Software selectable low power waveform
Flexible selection of frame frequency
Programmable blink mode and frequency on two segment terminals
Uses Only 32 kHz RTC clock source
On-chip LCD power supply
Software contrast adjustment control
Equal source and sink capability to Increase glass life time
Extended interrupt mode for display update or wake-up from sleep mode
Character
Mapping
Memory
Display
Timing
CAPH
Shadow
Memory
Display
LCD Power
Supply
CAPL
Control & Swap
Analog
Switch
Array
SEG[24:0]
COM[3:0]
VLCD
BIAS1
BIAS2
XMEGA B3
50