ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 26

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12. System Control and Reset
12.1
12.2
12.3
8074A–AVR–10/11
Features
Overview
Reset Sequence
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The reset system issues a microcontroller reset and sets the device to its initial state. This is for
situations where operation should not start or continue, such as when the microcontroller oper-
ates below its power supply rating. If a reset source goes active, the device enters and is kept in
reset until all reset sources have released their reset. The I/O pins are immediately tri-stated.
The program counter is set to the reset vector location, and all I/O registers are set to their initial
values. The SRAM content is kept. However, if the device accesses the SRAM when a reset
occurs, the content of the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated
before the device starts running from the reset vector address. By default, this is the lowest pro-
gram memory address, 0, but it is possible to move the reset vector to the lowest address in the
boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the
device. The software reset feature makes it possible to issue a controlled system reset from the
user software.
The reset status register has individual status flags for each reset source. It is cleared at power-
on reset, and shows which sources have issued a reset since the last power-on.
A reset request from any reset source will immediately reset the device and keep it in reset as
long as the request is active. When all reset requests are released, the device will go through
three stages before the device starts running again:
If another reset requests occurs during this process, the reset sequence will start over again.
•Reset counter delay
•Oscillator startup
•Oscillator calibration
Reset the microcontroller and set it to initial state when a reset source goes active
Multiple reset sources that cover different situations
Asynchronous operation
Reset status register for reading the reset source from the application code
– Power-on reset
– External reset
– Watchdog reset
– Brownout reset
– PDI reset
– Software reset
– No running system clock in the device is required for reset
XMEGA B3
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