ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 27

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.4
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
12.4.6
8074A–AVR–10/11
Reset Sources
Power-on Reset
Brownout Detection
External Reset
Watchdog Reset
Software Reset
Program and Debug Interface Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when
the V
sequence.
The POR is also activated to power down the device properly when the V
below the V
The V
teristics data.
The on-chip brownout detection (BOD) circuit monitors the V
paring it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled,
BOD is forced on at the lowest level during chip erase and when the PDI is enabled.
The external reset circuit is connected to the external RESET pin. The external reset will trigger
when the RESET pin is driven below the RESET pin threshold voltage, V
minimum pulse period, t
includes an internal pull-up resistor.
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the
WDT is not reset from the software within a programmable timout period, a watchdog reset will
be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator.
For more details see
The software reset makes it possible to issue a system reset from software by writing to the soft-
ware reset bit in the reset control register.The reset will be issued within two CPU clock cycles
after writing the bit. It is not possible to execute any instruction from when a software reset is
requested until it is issued.
The program and debug interface reset contains a separate reset source that is used to reset
the device during external programming and debugging. This reset source is accessible only
from external debuggers and programmers.
CC
POT
rises and reaches the POR threshold voltage (V
level is higher for falling V
POT
level.
”WDT – Watchdog Timer” on page
EXT
. The reset will be held as long as the pin is kept low. The RESET pin
CC
than for rising V
CC
. Consult the datasheet for POR charac-
28.
POT
CC
), and this will start the reset
level during operation by com-
RST
XMEGA B3
, for longer than the
CC
falls and drops
27