ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 298

• Manufacturer Part Number: ATxmega32A4
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.9.3
25.9.4
8077H–AVR–12/09
Single conversions on two ADC channels
Single conversions on two ADC channels, CH0 with gain
Figure 25-14. ADC timing for one single conversion with gain
Figure 25-15 on page 298
The pipelined design enables the second conversion to start on the next ADC clock cycle after t
the first conversion is started. In this example both conversions is triggered at the same time, but
for ADC Channel 1 (CH1) the actual start is not until the ADC sample and conversion of the MSB
for ADC Channel 0 (CH0) is done.
Figure 25-15. ADC timing for single conversions on two ADC channels
Figure 25-16 on page 299
nels where ADC Channel 0 uses the gain stage. As the gain stage introduce one addition cycle
for the gain sample and amplify, the sample for ADC Channel 1 is also delayed one ADC clock
cycle, until the ADC sample and MSB conversion is done for ADC Channel 0.
CONVERTING BIT CH0
CONVERTING BIT CH1
GAINSTAGE AMPLIFY
GAINSTAGE SAMPLE
CONVERTING BIT
ADC SAMPLE
ADC SAMPLE
START CH0
START CH1
CLK
CLK
IF CH0
IF CH1
START
ADC
ADC
IF
1
1
MSB
shows the conversion timing for single conversions on two ADC chan-
10
shows the ADC timing for single conversions on two ADC channels.
2
2
MSB
MSB
9
10
10
8
3
3
9
7
9
8
6
8
4
4
7
5
7
6
4
6
5
5
5
3
5
4
2
4
6
6
3
1
3
LSB
2
2
7
7
1
1
XMEGA A
LSB
LSB
8
8
9
9
298