ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 218
ATxmega32A4
Manufacturer Part Number
ATxmega32A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32A4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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19.9.2
8077H–AVR–12/09
CTRLB - TWI Master Control Register B
• Bit 4 - WIEN: Write Interrupt Enable
Setting the Write Interrupt Enable (WIEN) bit enables the Write Interrupt when the Write Interrupt
Flag (WIF) in the STATUS register is set. In addition the INTLVL bits must be unequal zero for
TWI master interrupts to be generated.
• Bit 3 - ENABLE: Enable TWI Master
Setting the Enable TWI Master (ENABLE) bit enables the TWI Master.
• Bit 2:0 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 7:4 - Reserved Bits
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 - TIMEOUT[1:0]: Inactive Bus Timeout
Setting the Inactive Bus Timeout (TIMEOUT) bits unequal zero will enable the inactive bus time-
out supervisor. If the bus is inactive for longer than the TIMEOUT settings, the bus state logic
will enter the idle state.
Figure 19-2
Table 19-2.
• Bit 1 - QCEN: Quick Command Enable
Setting the Quick Command Enable (QCEN) bit enables Quick Command. When Quick Com-
mand is enabled, a STOP condition is sent immediate after the slave acknowledges the
address.
• Bit 0 - SMEN: Smart Mode Enable
Setting the Smart Mode Enable (SMEN) bit enables Smart Mode. When Smart mode is enabled,
the Acknowledge Action, as set by the ACKACT bit in Control Register C, is sent immediately
after reading the DATA register.
Bit
+0x01
Read/Write
Initial Value
TIMEOUT[1:0]
00
01
10
11
lists the timeout settings.
7
R
0
-
TWI master inactive bus timeout settings
Group Configuration
6
R
0
-
DISABLED
100US
200US
50US
R
5
0
-
R
4
0
-
Description
Disabled, normally used for I
50 µs, normally used for SMBus at 100 kHz
R/W
3
0
TIMEOUT[1:0]
R/W
2
0
100 µs
200 µs
QCEN
R/W
2
1
0
C
XMEGA A
SMEN
R/W
0
0
CTRLB
218
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