ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 275
ATxmega32A4
Manufacturer Part Number
ATxmega32A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32A4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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24.8.4
24.8.5
24.8.6
24.9
8077H–AVR–12/09
Combined SRAM & SDRAM Configuration
Timing
Initialization
Refresh
Figure 24-9. 4-Port SDRAM configuration
The Clock Enable (CKE) signal is required for SDRAM when the EBI is clocked at 2x the CPU
clock speed.
Configuring Chip Select 3 to SDRAM will enable the initialization of the SDRAM. The “Load
Mode Register” command is automatically issued at the end of the initialization. For the correct
information to be loaded to the SDRAM, one must do one of the following:
1.
2.
initialized.
The SDRAM initialization is non-interruptible by other EBI accesses.
The EBI will automatically handle the refresh of the SDRAM as long as the refresh period is con-
figured. Refresh will be done as soon as available after the refresh counter reaches the period.
The EBI can collect up to 4 refresh commands in case the interface is busy on another chip
select or in the middle of a read/write at a time a refresh should have been performed.
Combined SRAM and SDRAM configuration enables the EBI to have both SDRAM and SRAM
connected at the same time. This only available for devices with 4 port EBI interface.
10 on page 276
Configure SDRAM control registers before enabling Chip Select 3 to SDRAM.
Issue a “Load Mode Register” command and perform a dummy-access after SDRAM is
EBI
shows the configuration with all interface signals.
CAS/RE
BA[1:0]
CS[3:0]
A[11:8]
A[7:0]]
D[7:0]
DQM
CKE
RAS
CLK
WE
CLK
CKE
BA[1:0]
DQM
WE
RAS
CAS
D[7:0]
A[7:0]
A[11:8]
CS
SDRAM
XMEGA A
Figure 24-
275
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