ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 212

• Manufacturer Part Number: ATxmega32A4
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.4
8077H–AVR–12/09
TWI Bus State Logic
device which first completes its high period (DEVICE1) forces the clock line low and the proce-
dure are then repeated. The result of this is that the device with the shortest clock period
determines the high period while the low period of the clock is determined by the longest clock
period.
The bus state logic continuously monitors the activity on the TWI bus lines when the master is
enabled. It continues to operate in all sleep modes, including Power down.
The bus state logic includes START and STOP condition detectors, collision detection, inactive
bus timeout detection, and bit counter. This is used to determine the bus state. Software can get
the current bus state by reading the Bus State bits in the Master Status register. The bus state
can be 'unknown', 'idle', 'busy' or 'owner' and is determined according to the state diagram
shown in
the figure.
Figure 19-11. Bus State, State Diagram
After a system reset, the bus state is unknown. From this the bus state machine can be forced to
enter idle by writing to the Bus State bits accordingly. If no state is set by application software
the bus state will become idle when a STOP condition is detected. If the Master Inactive Bus
Timeout is enabled the bus state will change to idle on the occurrence of a timeout. After a
known bus state is established the bus state will not re-enter the unknown state from any of the
other states. Only a system reset or disabling the TWI master will set the state to unknown.
When the bus is idle it is ready for a new transaction. If a START condition generated externally
is detected, the bus becomes busy until a STOP condition is detected. The STOP condition will
change the bus state to idle. If the Master Inactive Bus Timeout is enabled bus state will change
from busy to idle on the occurrence of a timeout.
Figure
19-11. The value of the Bus State bits according to state is shown in binary in
RESET
(0b01)
IDLE
P + Timeout
Write ADDRESS
UNKNOWN
(S)
(0b00)
Command P
P + Timeout
OWNER
(0b10)
S
ADDRESS(Sr)
Write
Arbitration
Lost
BUSY
(0b11)
Sr
XMEGA A
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