ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 97

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.10.4
7.10.5
8331A–AVR–07/11
XOSCFAIL – XOSC Failure Detection Register
RC32KCAL – 32kHz Oscillator Calibration Register
• Bit 7:4 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 3 – PLLFDIF: PLL Fault Detection Flag
If PLL failure detection is enabled, PLLFDIF is set when the PLL looses lock. Writing logic one to
this location will clear PLLFDIF.
• Bit 2 – PLLFDEN: PLL Fault Detection Enable
Setting this bit will enable PLL failure detection. A non-maskable interrupt will be issued when
PLLFDIF is set.
This bit is protected by the configuration change protection mechanism. Refer to
Change Protection” on page 12
• Bit 1 – XOSCFDIF: Failure Detection Interrupt Flag
If the external clock source oscillator failure monitor is enabled, XOSCFDIF is set when a failure
is detected. Writing logic one to this location will clear XOSCFDIF.
• Bit 0 – XOSCFDEN: Failure Detection Enable
Setting this bit will enable the failure detection monitor, and a non-maskable interrupt will be
issued when XOSCFDIF is set.
This bit is protected by the configuration change protection mechanism. Refer to
Change Protection” on page 12
by a reset.
• Bit 7:0 – RC32KCAL[7:0]: 32.768kHz Internal Oscillator Calibration Register
This register is used to calibrate the 32.768kHz internal oscillator. A factory-calibrated value is
loaded from the signature row of the device and written to this register during reset, giving an
oscillator frequency close to 32.768kHz. The register can also be written from software to cali-
brate the oscillator frequency during normal operation.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
R/W
7
x
7
–
R
0
R/W
6
R
x
6
–
0
R/W
for details.
for details. Once enabled, failure detection can only be disabled
R
5
5
–
0
x
R/W
4
–
R
0
4
RC32KCAL[7:0]
x
PLLFDIF
R/W
R/W
3
0
3
x
Atmel AVR XMEGA AU
PLLFDEN
R/W
R/W
2
0
2
x
XOSCFDIF
R/W
R/W
1
1
0
x
XOSCFDEN
R/W
R/W
0
x
0
0
”Configuration
”Configuration
RC32KCAL
XOSCFAIL
97