ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 197

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.10.6
15.10.7
8331A–AVR–07/11
INTCTRLB — Interrupt Enable Register B
CTRLF — Control Register F
• Bit 3:2 – UNFHINTLVL[1:0]: High Byte Timer Underflow Interrupt Level
These bits enable the High Byte Timer Underflow Interrupt and select the interrupt level as
described in
enabled interrupt will be triggered when the UNFHIF in the INTFLAGS register is set.
• Bit 1:0 – UNFLINTLVL[1:0]: Low Byte Timer Underflow Interrupt Level
These bits enable the Low Byte Timer Underflow Interrupt and select the interrupt level as
described in
enabled interrupt will be triggered when the UNFLIF in the INTFLAGS register is set.
• Bit 7:0 – CMPLxINTLVL[1:0]: Compare Low Byte x Interrupt Level
These bits enable the Low Byte Timer Compare Interrupt and select the interrupt level as
described in
enabled interrupt will be triggered when the CMPLxIF in the INTFLAGS register is set.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 – CMD[1:0]: Timer/Counter Command
These command bits are used for software control of update, restart, and reset of the
Timer/Counter. The command bits are always read as zero. The CMD bits must be used
together with CMDEN
Table 15-4.
Bit
+0x07
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
CMD
00
01
10
11
”Interrupts and Programmable Multilevel Interrupt Controller” on page
”Interrupts and Programmable Multilevel Interrupt Controller” on page
”Interrupts and Programmable Multilevel Interrupt Controller” on page
CMPLDINTLVL[1:0]
R/W
Command selections
7
0
R
7
–
0
NONE
—
RESTART
RESET
Group Configuration
R/W
R
6
0
6
–
0
CMPLCINTLVL[1:0]
R/W
R
5
–
0
5
0
4
–
R
0
Description
None
Reserved
Force Restart
Force Hard Reset (Ignored if T/C is not in “OFF“state)
R/W
4
0
R/W
3
0
Atmel AVR XMEGA AU
CMPLBINTLVL[1:0]
R/W
CMD[1:0]
3
0
R/W
2
0
R/W
2
0
R/W
1
0
CMDEN[1:0]
CMPLAINTLVL[1:0]
R/W
1
0
R/W
0
0
R/W
0
0
132. The
132. The
132. The
CTRLF
INTCTRLB
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