ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 211

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16.7.8
16.7.9
16.7.10
16.7.11
8331A–AVR–07/11
DTHS – Dead-time High Side Register
DTLSBUF – Dead-time Low Side Buffer Register
DTHSBUF – Dead-time High Side Buffer Register
OUTOVEN – Output Override Enable Register
• Bit 7:0 – DTLS: Dead-time Low Side
This register holds the number of peripheral clock cycles for the dead-time low side.
• Bit 7:0 – DTHS: Dead-time High Side
This register holds the number of peripheral clock cycles for the dead-time high side.
• Bit 7:0 – DTLSBUF: Dead-time Low Side Buffer
This register is the buffer for the DTLS register. If double buffering is used, valid content in this
register is copied to the DTLS register on an UPDATE condition.
• Bit 7:0 – DTHSBUF: Dead-time High Side Buffer
This register is the buffer for the DTHS register. If double buffering is used, valid content in this
register is copied to the DTHS register on an UPDATE condition.
Note:
Bit
+0x0A
Read/Write
Initial Value
Bit
+0x0B
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
Bit
+0x0C
Read/Write
Initial Value
1. Can be written only if the fault detect flag (FDF) is zero.
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
(1)
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
(1)
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
(1)
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
DTLSBUF[7:0]
DTHSBUF[7:0]
OUTOVEN[7:0]
(1)
DTHS[7:0]
R/W
R/W
R/W
Atmel AVR XMEGA AU
R/W
3
0
3
0
3
0
3
0
(1)
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
(1)
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
(1)
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
(1)
DTHSBUF
DTLSBUF
OUTOVEN
DTHS
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