ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 327

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.10.12 OFFSETCAL – DAC Offset Calibration Register
26.11 Register Summary
8077H–AVR–12/09
Address
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x07
+0x08
+0x09
+0x10
+0x11
+0x12
+0x13
+0x14
+0x15
+0x16
+0x17
+0x18
+0x19
+0x1A
+0x1B
Name
CTRLB
OFFSETCAL
CH0DATAH
CH1DATAH
CH0DATAL
CH1DATAL
TIMCTRL
GAINCAL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EVCTRL
STATUS
CTRLC
CTRLA
• Bits 6:0 - GAINCAL[6:0]: DAC Gain Calibration value
These bits are used to compensate the gain error in the DAC. See
details on how to calibrate gain.
• Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 6:0 - OFFSETCAL[6:0]: DAC Offset Calibration value
These bits are used to compensate the offset error in the DAC. See
for details on how to calibrate offset.
This is the I/O summary when the DAC is configured to give standard 12-bit results. I/O sum-
mary for 12-bit left adjusted will be similar, but with some changes in the data registers
CHnDATAL and CHnDATAH.
Bit
+0x09
Read/Write
Initial Value
Bit 7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit 6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CHSEL[1:0]
R
7
0
-
CONINTVAL[2:0]
Bit 5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
6
0
Bit 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
5
0
REFSEL[1:0]
CHDATA[7:0]
CHDATA[7:0]
CH1EN
Bit 3
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
OFFSETCAL[6:0]
4
0
GAINCAL[6:0]
OFFSETCAL[6:0]
R/W
CH0EN
3
0
Bit 2
-
-
-
-
-
-
-
-
-
-
-
-
-
REFRESH[3:0]
CHDATA[11:8]
CHDATA[11:8]
R/W
2
0
CH1TRIG
LPMODE
EVSEL[2:0]
CH1DRE
Bit 1
-
-
-
-
-
-
-
-
-
-
-
”Calibration” on page 319
R/W
”Calibration” on page 319
1
0
CH0TRIG
LEFTADJ
ENABLE
CH0DRE
XMEGA A
Bit 0
R/W
-
-
-
-
-
-
-
-
-
-
0
0
OFFSETCAL
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