ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 146
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ATxmega256A3
Manufacturer Part Number
ATxmega256A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega256A3
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.16 Register Description – Virtual Port
13.16.1
13.16.2
13.16.3
8077H–AVR–12/09
DIR - Data Direction
OUT - Data Output Value
IN - Data Input Value
Table 13-8.
• Bit 7:0 - DIR[7:0]: Data Direction Register
This register sets the data direction for the individual pins in the port mapped by "VPCTRLA -
Virtual Port-map Control Register A" or "VPCTRLB - Virtual Port-map Control Register B". When
a port is mapped as virtual, accessing this register is identical to accessing the actual DIR regis-
ter for the port.
• Bit 7:0 - OUT[7:0]: Data Output value
This register sets the data output value for the individual pins in the port mapped by "VPCTRLA
- Virtual Port-map Control Register A" or "VPCTRLB - Virtual Port-map Control Register B".
When a port is mapped as virtual, accessing this register is identical to accessing the actual
OUT register for the port.
Bit
+0x02
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
CLKOUT[1:0]
00
01
10
11
Bit
+0x00
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
Clock output configurations
R/W
R/W
R/W
6
0
6
0
6
0
Group Configuration
OFF
PC7
PD7
PE7
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
OUT[7:0]
DIR[7:0]
IN[7:0]
Description
Clock out disabled
Clock output on Port C pin 7
Clock output on Port D pin 7
Clock output on Port E pin 7
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
XMEGA A
R/W
R/W
R/W
0
0
0
0
0
0
OUT
DIR
IN
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