ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 281

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.11.3
24.11.4
24.11.5
8077H–AVR–12/09
REFRESH - SDRAM Refresh Period Register
INITDLY - SDRAM Initialization Delay Register
SDRAMCTRLB - SDRAM Control Register B
• Bit 15:10 - Reserved
These bits are reserved and will always be read as zero.
• Bit 9:0 - REFRESH[9:0]: SDRAM Refresh Period
This register sets the refresh period as a number of Peripheral 2x clock (CLK
EBI is busy with another external memory access at time of refresh, up to 4 refresh will be
remembered and given at the first available time.
• Bit 15:14 - Reserved
These bits are reserved and will always be read as zero.
• Bit 13:0 - INITDLY[13:0]: SDRAM Initialization Delay
This register is used to delay the initialisation sequence after the controller is enabled until all
voltages are stabilized and the SDRAM clock has been running long enough to take the SDRAM
chip through its initialisation sequence. The initialisation sequence includes pre-charge all banks
to their idle state issuing an auto-refresh cycle and then loading the mode register. The setting in
this register is as a number of Peripheral 2x clock cycles.
Bit
+0x04
+0x05
Read/Write
Initial Value
Bit
+0x06
+0x07
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
R/W
R/W
R/W
15
15
R
R
7
0
0
7
0
0
7
0
-
-
MRDLY[1:0]
R/W
R/W
R/W
14
14
R
R
6
0
0
6
0
0
6
0
-
-
R/W
R/W
R/W
R/W
13
13
R
5
0
5
0
0
5
0
0
-
ROWCYCDLY[2:0]
R/W
R/W
R/W
R/W
12
12
R
4
0
4
0
0
4
0
0
REFRESH[7:0]
-
INITDLY[7:0]
R/W
R/W
R/W
R/W
11
11
R
3
0
3
0
0
3
0
0
-
INITDLY[9:8]
R/W
R/W
R/W
R/W
10
10
R
2
0
2
0
0
2
0
0
-
RPDLY[2:0]
R/W
R/W
R/W
R/W
R/W
REFRESH[9:8]
1
0
1
9
0
0
1
9
0
0
R/W
R/W
R/W
R/W
R/W
0
0
0
8
0
0
0
8
0
0
XMEGA A
PER
) cycles. If the
SDRAMCTRLB
REFRESHL
REFRESHH
INITDLYL
INITDLYH
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