ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 324

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.10.6
26.10.7
8077H–AVR–12/09
STATUS – DAC Status Register
CH0DATAH – DAC Channel 0 Data Register High
Table 26-5.
The number of clock cycles selected multiplied with the period of the Peripheral clock gives the
DAC refresh time.
• Bits 7:2 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 - CH1DRE: DAC Channel 1 Data Register Empty
This bit indicates that the data register for channel 1 is empty, meaning that a new conversion
value may be written. If the bit is cleared, writing to the data register may cause losing a conver-
sion value. This bit is directly used for DMA Request.
• Bit 0 - CH0DRE: DAC Channel 0 Data register Empty
This bit indicates that the data register for channel 0 is empty, meaning that a new conversion
value may be written. If the bit is cleared, writing to the data register may cause losing a conver-
sion value.This bit is directly used for DMA Request.
The two registers CHnDATAH and CHnDATAL are the high byte and low byte respectively of the
12-bit value CHnDATA that is converted to an analog voltage on DAC channel n. By default, the
12 bits are distributed with 8 bits in CHnDATAL and 4 bits in 4 LSB position of CHnDATAH
(right-adjusted).To select left-adjusted data it is possible by setting the LEFTADJ bit in the
CTRLC register.
When this is selected, it is also possible to do 8-bit conversions by writing only CHnDATAH
register.
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Bit
+0x05
Read/Write
Initial Value
1101
1110
1111
R
7
0
-
DAC Channel refresh control selection (Continued)
Bit
+0x19
Read/Write
Read/Write
Initial Value
Initial Value
R
6
0
-
7
R/W
R
0
0
-
R
5
0
OFF
-
6
R/W
R
0
0
-
R
4
0
-
5
R/W
R
0
0
-
R
3
0
-
4
R/W
R
0
0
CHDATA[11:4]
-
R
2
0
-
3
R/W
R/W
Auto refresh off
0
0
Reserved
Reserved
CH1DRE
R/W
2
1
0
R/W
R/W
0
0
CHDATA[11:8]
XMEGA A
CH0DRE
1
R/W
0
0
R/W
R/W
0
0
STATUS
0
R/W
R/W
0
0
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