ATxmega192A3U Atmel Corporation, ATxmega192A3U Datasheet - Page 349
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ATxmega192A3U
Manufacturer Part Number
ATxmega192A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192A3U
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega192A3U-AU
Manufacturer:
MSDS
Quantity:
124
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27.11.2
8331A–AVR–07/11
CTRLB (SRAM) – Control Register B
Table 27-21. Address size encoding (Continued)
1.
• Bit 1:0 – MODE[1:0]: Chip Select Mode
These bits select the Chip Select Mode and decide what type of interface is used for the external
memory or peripheral according to
Table 27-22. Chip Select Mode selection
1.
This configuration options in this register depend on the Chip Select Mode configuration. The
register description below is valid when the Chip Select Mode is configured for SRAM or SRAM
LPC.
• Bit 7:3 – Reserved
These bits are reserved and will always be read as zero.
Bit
+0x01
Read/Write
Initial Value
ASIZE[4:0]
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
Other
MODE[1:0]
Entire available data space used.
SDRAM can only be selected for CS3
00
01
10
11
R
7
–
0
R
6
–
0
Group Configuration
8K
16K
32K
64K
128K
256K
512K
1M
2M
4M
8M
16M
Group Configuration
DISABLE
SRAM
LPC
SDRAM
R
5
–
0
Table 27-22 on page
R
4
–
0
Address Size
8KBytes
16KBytes
32KBytes
64KBytes
128KBytes
256KBytes
512KBytes
1MBytes
2MBytes
4MBytes
8MBytes
16MBytes
-
Description
Chip Select Disabled
Enable Chip Select for SRAM
Enable Chip Select for SRAM LPC
Enable Chip Select for SDRAM
R
3
–
0
Atmel AVR XMEGA AU
349.
(1)
R/W
2
0
Address Lines Compared
ADDR[23:13]
ADDR[23:14
ADDR[23:15]
ADDR[23:16]
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
ADDR[23:21]
ADDR[23:22]
ADDR[23]
-
Reserved
SRWS[2:0]
R/W
1
0
R/W
(1)
0
0
CTRLB
349
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