ATxmega192A3U Atmel Corporation, ATxmega192A3U Datasheet - Page 137
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ATxmega192A3U
Manufacturer Part Number
ATxmega192A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192A3U
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega192A3U-AU
Manufacturer:
MSDS
Quantity:
124
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12.7
12.8
12.8.1
12.8.2
8331A–AVR–07/11
Moving Interrupts Between Application and Boot Sections
Register Description
STATUS – PMIC Status Register
INTPRI – PMIC Priority Register
The interrupt vectors can be moved from the default location in the application section in flash to
the start of the boot section.
• Bit 7 – NMIEX: Non-Maskable Interrupt Executing
This flag is set if a non-maskable interrupt is executing. The flag will be cleared when returning
(RETI) from the interrupt handler.
• Bit 6:3 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 2 – HILVLEX: High-level Interrupt Executing
This flag is set when a high-level interrupt is executing or when the interrupt handler has been
interrupted by an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
• Bit 1 – MEDLVLEX: Medium-level Interrupt Executing
This flag is set when a medium-level interrupt is executing or when the interrupt handler has
been interrupted by an interrupt from higher level or an NMI. The flag will be cleared when
returning (RETI) from the interrupt handler.
• Bit 0 – LOLVLEX: Low-level Interrupt Executing
This flag is set when a low-level interrupt is executing or when the interrupt handler has been
interrupted by an interrupt from higher level or an NMI. The flag will be cleared when returning
(RETI) from the interrupt handler.
• Bit 7:0 – INTPRI: Interrupt Priority
When round-robin scheduling is enabled, this register stores the interrupt vector of the last
acknowledged low-level interrupt. The stored interrupt vector will have the lowest priority the
next time one or more low-level interrupts are pending. The register is accessible from software
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
NMIEX
R/W
R
7
0
7
0
R/W
R
6
–
0
6
0
R/W
R
5
–
0
5
0
R/W
R
4
–
0
4
0
INTPRI[7:0]
Atmel AVR XMEGA AU
R/W
R
3
–
0
3
0
HILVLEX
R/W
R
2
0
2
0
MEDLVLEX
R/W
R
1
0
1
0
LOLVLEX
R/W
R
0
0
0
0
STATUS
INTPRI
137
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