ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 55
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16A4U-AU
Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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5.13.5
5.14
5.14.1
8077H–AVR–12/09
Register Description – DMA Channel
TEMPL - DMA Temporary Register Low
CTRLA - DMA Channel Control Register A
• Bit 7:0 - TEMP[7:0]: DMA Temporary Register 0
This register is used when reading 24- and 16-bit registers in the DMA controller. Byte 1 of the
16/24-bit registers is stored here when it is written by the CPU. Byte 1 of the 16/24-bit registers
are stored when byte 0 is read by the CPU. This register can also be read and written from the
user software.
Reading and writing 16- and 24-bit registers requires special attention. Please see detailed
description in the AVR Core manual.
• Bit 7- CHEN: DMA Channel Enable
Setting this bit enables the DMA channel. This bit is automatically cleared when the transaction
is completed. If the DMA channel is enabled and this bit is written to zero, the CHEN bit is not
cleared before the internal transfer buffer is empty and the DMA transfer is aborted.
• Bit 6 - CHRST: DMA Channel Software Reset
Setting this bit enables the channel reset. This bit is automatically cleared when reset is com-
pleted. This bit can only be set when the DMA channel is disabled (CHEN = 0).
• Bit 5 - REPEAT: DMA Channel Repeat Mode
Setting this bit enables the repeat mode. In repeat mode, this bit is cleared by hardware in the
beginning of the last block transfer. The REPCNT register should be configured before setting
the REPEAT bit.
• Bit 4 - TRFREQ: DMA Channel Transfer Request
Setting this bit requests a data transfer on the DMA Channel. This bit is automatically cleared at
the beginning of the data transfer. Writing this bit does not have any effect unless the channel is
enabled.
• Bit 3 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
CHEN
R/W
R/W
7
0
7
0
CHRST
R/W
R/W
6
0
6
0
REPEAT
R/W
R/W
5
0
5
0
TRFREQ
R/W
R/W
4
0
4
0
DMTEMP[7:0]
R/W
3
0
R
3
0
-
SINGLE
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
BURSTLEN[1:0]
0
XMEGA A
R/W
R/W
0
0
0
0
TEMPL
CTRLA
55
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