ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 270
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16A4U-AU
Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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24.5
24.6
24.6.1
24.6.2
8077H–AVR–12/09
EBI Clock
SRAM Configuration
No Multiplexing
Multiplexing address byte 0 and 1
The EBI is clocked from the Peripheral 2x (Clk
frequency, but it can also run at two times the CPU Clock frequency. This can be used to lower
the EBI access time. Refer to
Peripheral 2x Clock and how to configure this.
For use with SRAM the EBI can be configured for various address multiplexing modes by using
external address latches, or with no multiplexing. When a limited number of pins on the device
are is available for the EBI, Address Latch Enable (ALE) signals are used to control external
latches that multiplex address lines from the EBI. The available configurations is shown in
tion 24.6.1 on page 270
the SRAM interface signals.
Table 24-1.
When no multiplexing is used, there is a one-to-one connection between the EBI and the SRAM.
No external address latches are used.
Figure 24-2. Non-multiplexed SRAM connection
When address byte 0 (A[7:0]) and address byte 1 (A[15:8]) are multiplexed, they are output from
the same port, and the ALE1 signal from the device control the address latch.
Signal
CS
WE
RE
ALE[2:0]
A[23:0]
D[7:0]
AD[7:0]
SRAM Interface signals
EBI
Description
Chip Select
Write Enable
Read Enable
Address Latch Enable
Address
Data bus
Combined Address and Data
A[21:16]
through
A[15:8]
D[7:0]
A[7:0]
”System Clock and Clock options” on page 76
Section 24.6.4 on page
2PER
) Clock. This clock can run at the CPU Clock
271.
Table 24-1 on page 270
D[7:0]
A[7:0]
A[15:8]
A[21:16]
SRAM
XMEGA A
for details the
describe
Sec-
270
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