ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 202
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16A4U-AU
Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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18.3.10
18.3.11
18.3.12
18.3.13
18.3.14
8077H–AVR–12/09
PER2 - Period Register 2
PER1 - Period Register 1
PER0 - Period Register 0
COMP3 - Compare Register 3
COMP2 - Compare Register 2
The COMP0, COMP1, COMP2 and COMP3 registers represents the 32-bit value COMP. COMP
is constantly compared with the counter value (CNT). A compare match will set the COMPIF in
the INTFLAGS register, and the optional interrupt is generated.
If the COMP value is higher than the PER value, no RTC Compare Match interrupt requests or
events will be generated
After writing the high byte of the COMP register, the condition for setting OVFIF and COMPIF,
as well as the Overflow and Compare Match Wakeup condition, will be disabled for the following
two RTC clock cycles.
Bit
+0x0A
Read/Write
Reset Value
Bit
+0x09
Read/Write
Reset Value
Bit
+0x08
Read/Write
Reset Value
Bit
+0x0F
Read/Write
Reset Value
Bit
+0x0E
Read/Write
Reset Value
R/W
R/W
R/W
R/W
R/W
7
7
7
7
7
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
6
6
6
6
6
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
5
5
5
5
5
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
4
4
4
4
COMP[31:24]
4
COMP[23:16]
0
0
0
0
0
PER[23:16]
PER[15:8]
PER[7:0]
R/W
R/W
R/W
R/W
R/W
3
3
3
3
3
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
2
2
2
2
2
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
0
0
0
0
0
XMEGA A
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
COMP3
COMP2
PER2
PER1
PER0
202
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