ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 240
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16A4U-AU
Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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21.4
8077H–AVR–12/09
Frame Formats
Leading edge is the first clock edge in a clock cycle. Trailing edge is the last clock edge in a
clock cycle.
Figure 21-4. UCPHA and INVEN data transfer timing diagrams.
Data transfer is frame based, where a serial frame consists of one character of data bits with
synchronization bits (start and stop bits), and an optional parity bit for error checking. Note that
this does not apply to SPI operation (See
The USART accepts all 30 combinations of the following as valid frame formats:
A frame starts with the start bit followed by the least significant data bit and all data bits ending
with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the first
stop bit. One frame can be directly followed by a start bit and a new frame, or the communication
line can return to idle (high) state.
of the frame formats. Bits inside brackets are optional.
Figure 21-5. Frame Formats
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
(IDLE)
St
0
INVEN=0
1
2
Figure 21-5 on page 240
3
4
Section 21.4.2 ”SPI Frame Formats” on page
FRAME
[5]
[6]
[7]
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
[8]
illustrates the possible combinations
[P]
Sp1 [Sp2]
INVEN=1
(St / IDLE)
XMEGA A
241).
240
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