ATxmega128A4U Atmel Corporation, ATxmega128A4U Datasheet - Page 424

• Manufacturer Part Number: ATxmega128A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.7
32.7.1
32.7.2
32.7.3
8331A–AVR–07/11
Register Description – PDI Control and Status Registers
STATUS
RESET
CTRL
–
–
Program and Debug Interface Control Register
–
Program and Debug Interface Reset Register
Program and Debug Interface Status Register
The PDIcontrol and status registers are accessible in the PDI control and status register space
(CSRS) using the LDCS and STCS instructions. The CSRS contains registers directly involved
in configuration and status monitoring of the PDI itself.
• Bit 7:2
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1
This status bit is set when the key signalling enables the NVM programming interface. The exter-
nal programmer can poll this bit to verify successful enabling. Writing the NVMEN bit disables
the NVM interface.
• Bit 0
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 7:0
When the reset signature, 0x59, is written to RESET, the device is forced into reset. The device
is kept in reset until RESET is written with a data value different from the reset signature. Read-
ing the lsb will return the status of the reset. The seven msbs will always return the value 0x00,
regardless of whether the device is in reset or not.
• Bit 7:3
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
–
–
–
–
–
NVMEN: Nonvolatile Memory Enable
Reserved Bit
Reserved
RESET[7:0]: Reset Signature
Reserved
R/W
R
R
7
–
0
7
0
7
–
0
R/W
R
R
6
–
0
6
0
6
–
0
R/W
R
R
5
–
0
5
0
5
–
0
R/W
R
R
4
–
0
4
0
4
–
0
RESET[7:0]
Atmel AVR XMEGA AU
R/W
R
R
3
–
0
3
0
3
–
0
R/W
R/W
R
2
–
0
2
0
2
0
GUARDTIME[2:0]
NVMEN
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R
0
–
0
0
0
0
0
STATUS
RESET
CTRL
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