ATxmega128A4U Atmel Corporation, ATxmega128A4U Datasheet - Page 265

• Manufacturer Part Number: ATxmega128A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.3.9
21.4
8331A–AVR–07/11
TWI Bus State Logic
Synchronization
Figure 21-9
devices are able to issue a START condition, but DEVICE1 loses arbitration when attempting to
transmit a high level (bit 5) while DEVICE2 is transmitting a low level.
Arbitration between a repeated START condition and a data bit, a STOP condition and a data
bit, or a repeated START condition and a STOP condition are not allowed and will require spe-
cial handling by software.
A clock synchronization algorithm is necessary for solving situations where more than one mas-
ter is trying to control the SCL line at the same time. The algorithm is based on the same
principles used for the clock stretching previously described.
where two masters are competing for control over the bus clock. The SCL line is the wired-AND
result of the two masters clock outputs.
Figure 21-10. Clock synchronization.
A high-to-low transition on the SCL line will force the line low for all masters on the bus, and they
will start timing their low clock period. The timing length of the low clock period can vary among
the masters. When a master (DEVICE1 in this case) has completed its low period, it releases the
SCL line. However, the SCL line will not go high until all masters have released it. Consequently,
the SCL line will be held low by the device with the longest low period (DEVICE2). Devices with
shorter low periods must insert a wait state until the clock is released. All masters start their high
period when the SCL line is released by all devices and has gone high. The device which first
completes its high period (DEVICE1) forces the clock line low, and the procedure is then
repeated. The result is that the device with the shortest clock period determines the high period,
while the low period of the clock is determined by the device with the longest clock period.
The bus state logic continuously monitors the activity on the TWI bus lines when the master is
enabled. It continues to operate in all sleep modes, including power-down.
The bus state logic includes START and STOP condition detectors, collision detection, inactive
bus timeout detection, and a bit counter. Theseare used to determine the bus state. Software
can get the current bus state by reading the bus state bits in the master status register. The bus
state can be unknown, idle, busy, or owner, and is determined according to the state diagram
shown in
the figure.
DEVICE1_SCL
DEVICE2_SCL
SCL
(wired-AND)
Figure
shows an example where two TWI masters are contending for bus ownership. Both
21-11. The values of the bus state bits according to state are shown in binary in
Low Period
Count
State
Wait
Atmel AVR XMEGA AU
High Period
Count
Figure 21-10
shows an example
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