ATxmega128A4U Atmel Corporation, ATxmega128A4U Datasheet - Page 239

• Manufacturer Part Number: ATxmega128A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.6
8331A–AVR–07/11
Ping-Pong Operation
Figure 20-7. Clock Generation Configuration
When an endpoint is configured for ping-pong operation, it uses input direction's data buffer and
output direction's data buffer to create a single, double buffered endpoint, that can be set in input
or output direction. This give double buffered communication as the CPU or DMA can access
one of the buffers, while the other buffer is processing an on-going transfer. Ping-pong operation
is identical to the IN and OUT transactions described above, unless otherwise noted in this sec-
tion. Ping-pong operation is not possible for control endpoints.
When ping-pong operation is enabled for an endpoint, the endpoint in the opposite direction
must be disabled. The data buffer, data pointer, byte counter and auxiliary data from the enabled
endpoint are used as Bank 0, and correspondingly Bank 1 from the opposite endpoint direction.
The Bank Select (BANK) flag in the endpoint STATUS register indicates which data bank will be
used in the next transaction. It is updated after each transaction. TRNCOMPL0/TRNCOMPL1,
Underflow/Overflow (UDF/OVF) and CRC flags in the STATUS register are set for either the
enabled or the opposite endpoint direction according to the BANK flag. The Data Toggle (TOG-
GLE), Data Buffer 0/1 Not Acknowledge (BUSNACK0 and BUSNACK1) and BANK flags are
updated for the enabled endpoint direction only.
USB module
48MHz for full speed
6MHz low speed
USB clock
prescaler
USBPSDIV
Atmel AVR XMEGA AU
USBSRC
48MHz Internal Oscillator
PLL
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