ATtiny261 Atmel Corporation, ATtiny261 Datasheet - Page 77

• Manufacturer Part Number: ATtiny261
• Manufacturer: Atmel Corporation

Specifications of ATtiny261

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.6.1
11.6.2
11.7
Table 11-3.
2588E–AVR–08/10
Mode
0
1
2
3
4
Modes of Operation
Compare Match Blocking by TCNT0 Write
Using the Output Compare Unit
ICEN0
0
0
0
1
1
Modes of operation
TCW0
0
0
1
0
1
OCF0B, but in 16-bit mode the match can set only the Output Compare Flag OCF0A as there is
only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Compare
Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared
when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a log-
ical one to its I/O bit location.
Figure 11-5. Output Compare Unit, Block Diagram
All CPU write operations to the TCNT0H/L Register will block any Compare Match that occur in
the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A/B to be
initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter
clock is enabled.
Since writing TCNT0H/L will block all Compare Matches for one timer clock cycle, there are risks
involved when changing TCNT0H/L when using the Output Compare Unit, independently of
whether the Timer/Counter is running or not. If the value written to TCNT0H/L equals the
OCR0A/B value, the Compare Match will be missed.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the Timer/Counter Width (TCW0), Input Capture Enable (ICEN0) and Wave Genera-
tion Mode (CTC0) bits. See
Table 11-3
CTC0
X
X
X
0
1
summarises the different modes of operation.
Mode of Operation
Normal, 8-bit Mode
CTC Mode, 8-bit
Normal, 16-bit Mode
Input Capture Mode, 8-bit
Input Capture Mode, 16-bit
OCRnx
“TCCR0A – Timer/Counter0 Control Register A” on page
Figure 11-5
=
(8/16-bit Comparator )
DATA BUS
OCFnx (Int.Req.)
shows a block diagram of the Output Compare unit.
0xFFFF
0xFFFF
OCR0A
0xFF
0xFF
TOP
Update of OCRx at
Immediate
Immediate
Immediate
Immediate
Immediate
TCNTn
TOV Flag Set on
MAX (0xFFFF)
MAX (0xFFFF)
MAX (0xFF)
MAX (0xFF)
MAX (0xFF)
84.
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