ATtiny167 Automotive Atmel Corporation, ATtiny167 Automotive Datasheet - Page 273

• Manufacturer Part Number: ATtiny167 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny167 Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7728G–AVR–06/10
Mnemonics
BREAK
MOVW
SLEEP
SWAP
BCLR
PUSH
BSET
WDR
ROR
MOV
SPM
OUT
POP
NOP
LSR
ROL
ASR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SES
CLS
SEV
SET
SEH
CLH
LDD
LDD
LDS
STD
STD
STS
LPM
LPM
LPM
CLV
CLT
SEI
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
IN
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Rd, Z+
Y+q,Rr
Z+q,Rr
Rd, Z+
Rd, Rr
Rd, Rr
X+, Rr
- X, Rr
Y+, Rr
Rd, -Z
- Y, Rr
Z+, Rr
Rd, K
Rd, X
Rd, Y
-Z, Rr
Rd, P
Rd, b
Rd, Z
Rd, k
X, Rr
Rd, Z
Rr, b
Y, Rr
Z, Rr
k, Rr
P, Rr
Rd
Rd
Rd
Rd
Rd
Rd
Rr
s
s
Load Program Memory and Post-Inc
Clear Twos Complement Overflow
Set Twos Complement Overflow.
Store Indirect with Displacement
Store Indirect with Displacement
Load Indirect with Displacement
Load Indirect with Displacement
Clear Half Carry Flag in SREG
Set Half Carry Flag in SREG
Rotate Right Through Carry
Bit Store from Register to T
Store Indirect and Pre-Dec.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Post-Inc.
Rotate Left Through Carry
Bit load from T to Register
Move Between Registers
Pop Register from Stack
Load Direct from SRAM
Global Interrupt Disable
Store Program Memory
Push Register on Stack
Global Interrupt Enable
Load Program Memory
Load Program Memory
Clear Signed Test Flag
Store Direct to SRAM
Arithmetic Shift Right
Set Signed Test Flag
Copy Register Word
Clear Negative Flag
DATA TRANSFER INSTRUCTIONS
Description
Logical Shift Right
Set Negative Flag
Clear T in SREG
Load Immediate
Watchdog Reset
Clear Zero Flag
MCU CONTROL INSTRUCTIONS
Set T in SREG
Swap Nibbles
Set Zero Flag
Store Indirect
Store Indirect
Store Indirect
No Operation
Load Indirect
Load Indirect
Load Indirect
Clear Carry
Flag Clear
Set Carry
Flag Set
Out Port
In Port
Sleep
Break
(see specific descr. for Sleep function)
Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0)
(see specific descr. for WDR/timer)
Rd(0) C,Rd(n+1) Rd(n),C Rd(7)
Rd(7) C,Rd(n) Rd(n+1),C Rd(0)
Rd(n)
Rd(n)
For On-chip Debug Only
Rd+1:Rd
Rd
Rd
X
Y
(X)
(Y)
Z
X
Y
(Z)
Z
Rd
Rd
Operation
SREG(s)
SREG(s)
Rd
Rd
Rd
STACK
(Y + q)
(Z + q)
(Z)
Rd(n+1), Rd(7)
X - 1, Rd
Y - 1, Rd
Z - 1, Rd
X - 1, (X)
Y - 1, (Y)
Z - 1, (Z)
Rd(b)
T
Rd
Rd
Rd
(X), X
(Y), Y
Rd
(X)
(Y)
R0
Rd
Rd(n+1), n=0..6
Rd
Rd
(Z)
(k)
Rr, X
Rr, Y
Rr, Z
Rd
(Z), Z
(Z), Z
P
C
C
N
N
S
S
V
V
H
H
Z
Z
T
T
I
I
(Y + q)
STACK
Rr(b)
(Z + q)
R1:R0
ATtiny87/ATtiny167
Rr
1
0
(X)
(Y)
(Z)
(Z)
(Z)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Rr
Rr
Rr
(k)
Rr
Rr
Rr+1:Rr
P
K
T
Rr
Rr
Rr
Y + 1
Z + 1
X + 1
X + 1
Y + 1
Z+1
Z+1
1
0
(X)
(Y)
(Z)
Rr
Rr
Rr
0
Flags
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
#Clock
N/A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
2
2
1
1
1
-
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