ATtiny167 Automotive Atmel Corporation, ATtiny167 Automotive Datasheet - Page 148
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ATtiny167 Automotive
Manufacturer Part Number
ATtiny167 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY167_AUTOMOTIVE.pdf
(10 pages)
3.ATTINY167_AUTOMOTIVE.pdf
(283 pages)
Specifications of ATtiny167 Automotive
Flash (kbytes)
16 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY167_AUTOMOTIVE PDF datasheet #2
- ATTINY167_AUTOMOTIVE PDF datasheet #3
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- Download datasheet (5Mb)
13.3
148
Data Modes
ATtiny87/ATtiny167
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
ure 13-3
SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum-
marizing
Table 13-5.
Figure 13-3. SPI Transfer Format with CPHA = 0
Figure 13-4. SPI Transfer Format with CPHA = 1
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
SS
Table 13-2
and
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB first (DORD = 0)
LSB first (DORD = 1)
Figure
CPOL Functionality
and
13-4. Data bits are shifted out and latched in on opposite edges of the
Table
MSB
LSB
MSB
LSB
13-3, as done below:
Sample (Falling)
Bit 6
Bit 1
Sample (Rising)
Leading Edge
Setup (Falling)
Setup (Rising)
Bit 6
Bit 1
Bit 5
Bit 2
Bit 5
Bit 2
Bit 4
Bit 3
Bit 4
Bit 3
Bit 3
Bit 4
Sample (Falling)
Sample (Rising)
Bit 3
Bit 4
Setup (Falling)
Setup (Rising)
Trailing Edge
Bit 2
Bit 5
Bit 2
Bit 5
Bit 1
Bit 6
Bit 1
Bit 6
LSB
MSB
7728G–AVR–06/10
LSB
MSB
SPI Mode
0
1
2
3
Fig-
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