ATtiny167 Automotive Atmel Corporation, ATtiny167 Automotive Datasheet - Page 182

• Manufacturer Part Number: ATtiny167 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny167 Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6.2
182
ATtiny87/ATtiny167
LIN Status and Interrupt Register - LINSIR
• Bits 7:5 - LIDST[2:0]: Identifier Status
• Bit 4 - LBUSY: Busy Signal
• Bit 3 - LERR: Error Interrupt
• Bit 2 - LIDOK: Identifier Interrupt
• Bit 1 - LTXOK: Transmit Performed Interrupt
Initial Value
Read/Write
enable bit - LENERR - is set in LINENIR.
resets all LINERR bits.
LINENIR.
Bit
– 0xx = no specific identifier,
– 100 = Identifier 60 (0x3C),
– 101 = Identifier 61 (0x3D),
– 110 = Identifier 62 (0x3E),
– 111 = Identifier 63 (0x3F).
– 0 = Not busy,
– 1 = Busy (receiving or transmitting).
– 0 = No error,
– 1 = An error has occurred.
– 0 = No identifier,
– 1 = Slave task: Identifier present, master task: Tx Header complete.
– 0 = No Tx,
– 1 = Tx Response complete.
It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective
The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also
In UART mode, this bit is also cleared by reading LINDAT.
This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR.
The user clears this bit by writing 1, in order to reset this interrupt.
This bit generates an interrupt if its respective enable bit - LENTXOK - is set in
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by writing LINDAT.
LIDST2
R
7
0
LIDST1
R
6
0
LIDST0
R
5
0
LBUSY
R
4
0
R/Wone
LERR
3
0
R/Wone
LIDOK
2
0
R/Wone
LTXOK
1
0
R/Wone
LRXOK
0
0
7728G–AVR–06/10
LINSIR