ATtiny167 Automotive Atmel Corporation, ATtiny167 Automotive Datasheet - Page 108
ATtiny167 Automotive
Manufacturer Part Number
ATtiny167 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY167_AUTOMOTIVE.pdf
(10 pages)
3.ATTINY167_AUTOMOTIVE.pdf
(283 pages)
Specifications of ATtiny167 Automotive
Flash (kbytes)
16 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
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108
ATtiny87/ATtiny167
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock
cycles from an edge has been applied to the T1 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is
generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
tor uses sampling, the maximum frequency of an external clock it can detect is half the
sampling frequency (Nyquist sampling theorem). However, due to variation of the system
clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capaci-
tors) tolerances, it is recommended that maximum frequency of an external clock source is
less than f
An external clock source can not be prescaled.
Figure 11-2. Prescaler for Timer/Counter1
Note:
1. The synchronization logic on the input pin (
clk_I/O
CLK
PSRn
Tn
I/O
/2.5.
Synchronization
ExtClk
< f
clk_I/O
CSn0
CSn1
CSn2
/2) given a 50/50 % duty cycle. Since the edge detec-
Clear
(1)
TIMER/COUNTERn CLOCK SOURCE
0
10-BIT T/C PRESCALER
T
1
)
is shown in
clk
Tn
Figure
11-1.
7728G–AVR–06/10
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