ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 97

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ATtiny167

Manufacturer Part Number
ATtiny167
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny167

Flash (kbytes)
16 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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10.8
8265B–AVR–09/10
Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock
(clk
replaced by the Timer/Counter Oscillator clock. The figures include information on when inter-
rupt flags are set.
figure shows the count sequence close to the MAX value in all modes other than phase correct
PWM mode.
Figure 10-8. Timer/Counter Timing Diagram, no Prescaling
Figure 10-9
Figure 10-9. Timer/Counter Timing Diagram, with Prescaler (f
Figure 10-10
Figure 10-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f
TCNTn
TCNTn
TCNTn
(clk
(clk
(clk
OCRnx
TOVn
TOVn
OCFnx
clk
clk
clk
T
clk
clk
clk
0) is therefore shown as a clock enable signal. In asynchronous mode, clk
I/O
I/O
I/O
I/O
I/O
I/O
Tn
Tn
Tn
/1)
/8)
/8)
shows the same timing data, but with the prescaler enabled.
shows the setting of OCF0A in all modes except CTC mode.
Figure 10-8
OCRnx - 1
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation. The
OCRnx
MAX
MAX
OCRnx Value
OCRnx + 1
BOTTOM
BOTTOM
clk_I/O
/8)
BOTTOM + 1
BOTTOM + 1
OCRnx + 2
I/O
clk_I/O
should be
/8)
97

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