ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 154

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

154
ATtiny87/ATtiny167
Figure 14-4. Two-wire Mode Operation, Simplified Diagram
Figure 14-4
Slave. It is only the physical layer that is shown since the system operation is highly depen-
dent of the communication scheme used. The main differences between the Master and Slave
operation at this level, is the serial clock generation which is always done by the Master, and
only the Slave uses the clock control unit. Clock generation must be implemented in software,
but the shift operation is done automatically by both devices. Note that only clocking on nega-
tive edge for shifting data is of practical use in this mode. The slave can insert wait states at
start or end of transfer by forcing the SCL clock low. This means that the Master must always
check if the SCL line was actually released after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that
the transfer is completed. The clock is generated by the master by toggling the USCK pin via
the PORT Register.
The data direction is not given by the physical layer. A protocol, like the one used by the
TWI-bus, must be implemented to control the data flow.
Figure 14-5. Two-wire Mode, Typical Timing Diagram
SDA
SCL
SLAVE
MASTER
Bit7
Bit7
S
A B
shows two USI units operating in Two-wire mode, one as Master and one as
Bit6
Bit6
C
ADDRESS
Bit5
Bit5
1 - 7
Bit4
Bit4
Bit3
Bit3
R/W
8
Bit2
Bit2
D
Bit1
Bit1
ACK
9
Bit0
Bit0
E
DATA
1 - 8
Two-wire Clock
Control Unit
ACK
9
PORTxn
HOLD
DATA
SCL
1 - 8
SDA
SCL
SDA
SCL
ACK
9
VCC
8265B–AVR–09/10
F
P