ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 93

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.7.1
10.7.2
8265B–AVR–09/10
Normal Mode
Clear Timer on Compare Match (CTC) Mode
For detailed timing information refer to
The simplest mode of operation is the Normal mode (WGM0[1:0] = 0). In this mode the count-
ing direction is always up (incrementing), and no counter clear is performed. The counter
simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from
the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in
the same timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves
like a ninth bit, except that it is only set, not cleared. However, combined with the timer over-
flow interrupt that automatically clears the TOV0 flag, the timer resolution can be increased by
software. There are no special cases to consider in the Normal mode, a new counter value
can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM0[1:0] = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the coun-
ter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter,
hence also its resolution. This mode allows greater control of the compare match output fre-
quency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
increases until a compare match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.
Figure 10-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using
the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updat-
ing the TOP value. However, changing the TOP to a value close to BOTTOM when the
counter is running with none or a low prescaler value must be done with care since the CTC
mode does not have the double buffering feature. If the new value written to OCR0A is lower
than the current value of TCNT0, the counter will miss the compare match. The counter will
then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the
compare match can occur.
TCNTn
OCnx
(Toggle)
Period
1
2
“Timer/Counter Timing Diagrams” on page
3
4
Figure
10-5. The counter value (TCNT0)
OCnx Interrupt Flag Set
(COMnx1:0 = 1)
97.
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