ATmega8515 Atmel Corporation, ATmega8515 Datasheet - Page 96
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ATmega8515
Manufacturer Part Number
ATmega8515
Description
Manufacturer
Atmel Corporation
Specifications of ATmega8515
Flash (kbytes)
8 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
35
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Special Function IO Register –
SFIOR
96
ATmega8515(L)
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than f
An external clock source can not be prescaled.
Figure 46. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be
reset. The bit will be cleared by hardware after the operation is performed. Writing a
zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share
the same prescaler and a reset of this prescaler will affect both timers. This bit will
always be read as zero.
PSR10
Bit
Read/Write
Initial Value
clk
T0
T1
I/O
Synchronization
Synchronization
1. The synchronization logic on the input pins (
R/W
7
–
0
XMBK
R/W
6
0
XMM2
R/W
5
0
clk_I/O
clk
Clear
T1
/2.5.
XMM1
R/W
4
0
XMM0
R/W
3
0
T1/T0)
PUD
R/W
is shown in Figure 45.
2
0
(1)
R/W
1
–
0
clk
PSR10
R/W
T0
2512K–AVR–01/10
0
0
SFIOR