ATmega640 Atmel Corporation, ATmega640 Datasheet - Page 23
ATmega640
Manufacturer Part Number
ATmega640
Description
Manufacturer
Atmel Corporation
Specifications of ATmega640
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
86
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
1
Uart
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
16
Input Capture Channels
4
Pwm Channels
15
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Quantity
Price
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ATMEL/爱特梅尔
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56
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8.2.1
8.3
2549N–AVR–05/11
EEPROM Data Memory
Data Memory Access Times
Figure 8-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 8-3.
The ATmega640/1280/1281/2560/2561 contains 4Kbytes of data EEPROM memory. It is orga-
nized as a separate data space, in which single bytes can be read and written. The EEPROM
has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and
the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
“Serial Downloading” on page
“Programming the EEPROM” on page 343
Address (HEX)
60 - 1FF
20 - 5F
0 - 1F
FFFF
Address
21FF
2200
200
clk
Data Memory Map
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
Compute Address
349,
ATmega640/1280/1281/2560/2561
T1
Memory Access Instruction
416 External I/O Registers
“Programming via the JTAG Interface” on page
64 I/O Registers
External SRAM
Internal SRAM
32 Registers
(0 - 64K × 8)
respectively.
(8192 × 8)
Address valid
CPU
T2
cycles as described in
Next Instruction
T3
Figure
8-3.
354, and
23
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