ATmega640 Atmel Corporation, ATmega640 Datasheet - Page 113
ATmega640
Manufacturer Part Number
ATmega640
Description
Manufacturer
Atmel Corporation
Specifications of ATmega640
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
86
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
1
Uart
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
16
Input Capture Channels
4
Pwm Channels
15
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Part Number
Manufacturer
Quantity
Price
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Manufacturer:
OSRAM
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12 000
Part Number:
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Manufacturer:
ATMEL/爱特梅尔
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56
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15.2
15.2.1
2549N–AVR–05/11
Register Description
EICRA – External Interrupt Control Register A
Figure 15-1. Normal pin change interrupt.
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 7:0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in
asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in
on page 114
rupt. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will
generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an
interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt
Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt
flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Regis-
ter before the interrupt is re-enabled.
PCINT(0)
Bit
(0x69)
Read/Write
Initial Value
pcint_setflag
pcint_in_(n)
clk
PCINT(n)
pcint_syn
pin_sync
pin_lat
PCIF
will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
LE
clk
ISC31
R/W
7
0
pin_lat
D
Q
ISC30
R/W
pin_sync
PCINT(0) in PCMSK(x)
6
0
ATmega640/1280/1281/2560/2561
ISC21
pcint_in_(0)
R/W
5
0
Table 15-1 on page
ISC20
R/W
4
0
0
x
clk
ISC11
R/W
3
0
114. Edges on INT3:0 are registered
pcint_syn
ISC10
R/W
2
0
ISC01
pcint_setflag
R/W
1
0
ISC00
R/W
0
0
PCIF
Table 15-2
EICRA
113
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