ATmega640 Atmel Corporation, ATmega640 Datasheet - Page 160
ATmega640
Manufacturer Part Number
ATmega640
Description
Manufacturer
Atmel Corporation
Specifications of ATmega640
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
86
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
1
Uart
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
16
Input Capture Channels
4
Pwm Channels
15
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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17.11.5
17.11.6
17.11.7
17.11.8
2549N–AVR–05/11
TCCR1B – Timer/Counter 1 Control Register B
TCCR3B – Timer/Counter 3 Control Register B
TCCR4B – Timer/Counter 4 Control Register B
TCCR5B – Timer/Counter 5 Control Register B
Table 17-5
correct and frequency correct PWM mode.
Table 17-5.
Note:
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is
activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The input capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
Bit
(0x81)
Read/Write
Initial Value
Bit
(0x91)
Read/Write
Initial Value
Bit
(0xA1)
Read/Write
Initial Value
Bit
(0x121)
Read/Write
Initial Value
COMnA1
COMnB1
COMnC1
0
0
1
1
A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1//COMnC1 is set.
details.
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
COMnA0
COMnB0
COMnC0
Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
ICNC1
ICNC3
ICNC4
ICNC5
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
0
1
0
1
ICES1
ICES4
ICES5
ICES3
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
disconnected (normal port operation). For all other WGM1 settings, normal
WGM13:0 =9 or 11: Toggle OC1A on Compare Match, OC1B and OC1C
Clear OCnA/OCnB/OCnC on compare match when downcounting
Clear OCnA/OCnB/OCnC on compare match when up-counting
Set OCnA/OCnB/OCnC on compare match when downcounting
ATmega640/1280/1281/2560/2561
Set OCnA/OCnB/OCnC on compare match when up-counting
Normal port operation, OCnA/OCnB/OCnC disconnected
R
R
R
R
5
–
0
5
–
0
5
–
0
5
–
0
port operation, OC1A/OC1B/OC1C disconnected
See “Phase Correct PWM Mode” on page 152.
WGM13
WGM33
WGM43
WGM53
R/W
R/W
R/W
R/W
4
0
0
4
0
4
0
4
WGM12
WGM42
WGM52
WGM32
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
Description
CS42
CS52
CS12
CS32
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
CS11
CS41
CS51
CS31
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
CS10
CS40
CS50
CS30
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
for more
TCCR1B
TCCR4B
TCCR5B
TCCR3B
160
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