ATmega640 Atmel Corporation, ATmega640 Datasheet - Page 161

• Manufacturer Part Number: ATmega640
• Manufacturer: Atmel Corporation

Specifications of ATmega640

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 86
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 4
• Pwm Channels: 15
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.11.9
2549N–AVR–05/11
TCCR1C – Timer/Counter 1 Control Register C
• Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the input cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
• Bit 4:3 – WGMn3:2: Waveform Generation Mode
See TCCRnA Register description.
• Bit 2:0 – CSn2:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
17-10 on page 156
Table 17-6.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
Bit
(0x82)
Read/Write
Initial Value
CSn2
0
0
0
0
1
1
1
1
CSn1
0
0
1
1
0
0
1
1
Clock Select Bit Description
FOC1A
W
7
0
and
CSn0
Figure 17-11 on page
FOC1B
0
1
0
1
0
1
0
1
W
6
0
ATmega640/1280/1281/2560/2561
FOC1C
W
5
0
External clock source on Tn pin. Clock on falling edge
External clock source on Tn pin. Clock on rising edge
No clock source. (Timer/Counter stopped)
R
4
–
0
156.
clk
clk
clk
clk
I/O
clk
R
I/O
3
–
0
I/O
I/O
/1024 (From prescaler)
/256 (From prescaler)
I/O
/64 (From prescaler)
/8 (From prescaler)
Description
/1 (No prescaling
R
2
–
0
R
1
0
–
R
0
–
0
TCCR1C
Figure
161