ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 314

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Data Registers
Reset Register
Programming Enable
Register
2490Q–AVR–06/10
The data registers are selected by the JTAG instruction registers described in section
ming Specific JTAG Instructions” on page
operations are:
•
•
•
•
•
The Reset Register is a Test Data Register used to reset the part during programming. It is
required to reset the part before entering programming mode.
A high value in the Reset Register corresponds to pulling the External Reset low. The part is
reset as long as there is a high value present in the Reset Register. Depending on the Fuse set-
tings for the clock options, the part will remain reset for a Reset Time-out Period (refer to
Sources” on page
latched, so the reset will take place immediately, as shown in
The Programming Enable Register is a 16-bit register. The contents of this register is compared
to the programming enable signature, binary code 1010_0011_0111_0000. When the contents
of the register is equal to the programming enable signature, programming via the JTAG port is
enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving
Programming mode.
Figure 150. Programming Enable Register
Reset Register
Programming Enable Register
Programming Command Register
Virtual Flash Page Load Register
Virtual Flash Page Read Register
38) after releasing the Reset Register. The output from this data register is not
TDO
TDI
D
A
T
A
$A370
ClockDR & PROG_ENABLE
=
311. The data registers relevant for programming
D
Q
Programming Enable
Figure 126 on page
ATmega64(L)
256.
“Program-
“Clock
314