ATmega32C1 Automotive Atmel Corporation, ATmega32C1 Automotive Datasheet - Page 285

• Manufacturer Part Number: ATmega32C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega32C1 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

24.6
7647G–AVR–09/11
Addressing the Flash During Self-Programming
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is exe-
cuted within four clock cycles. The CPU is halted during the entire Page Write operation if the
NRWW section is addressed.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four
clock cycles executes Page Erase. The page address is taken from the high part of the
Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion
of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is
halted during the entire Page Write operation if the NRWW section is addressed.
• Bit 0 – SPMEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together
with either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a
special meaning, see description above. If only SPMEN is written, the following SPM instruc-
tion will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The
LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM
instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase
and Page Write, the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
The Z-pointer is used to address the SPM commands.
Since the Flash is organized in pages (see
can be treated as having two different sections. One section, consisting of the least significant
bits, is addressing the words within a page, while the most significant bits are addressing the
pages. This is1 shown in
are addressed independently. Therefore it is of major importance that the Boot Loader soft-
ware addresses the same page in both the Page Erase and Page Write operation. Once a
programming operation is initiated, the address is latched and the Z-pointer can be used for
other operations.
The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits.
The content of the Z-pointer is ignored and will have no effect on the operation. The LPM
instruction does also use the Z-pointer to store the address. Since this instruction addresses
the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
Bit
ZH (R31)
ZL (R30)
Z15
Z7
15
7
Z14
Z6
14
Figure
6
24-3. Note that the Page Erase and Page Write operations
Z13
Z5
13
5
Atmel ATmega16/32/64/M1/C1
Z12
Z4
12
4
Table 25-12 on page
Z11
Z3
11
3
Z10
Z2
10
2
303), the Program Counter
Z9
Z1
9
1
Z8
Z0
8
0
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