ATmega329PA Atmel Corporation, ATmega329PA Datasheet - Page 264
ATmega329PA
Manufacturer Part Number
ATmega329PA
Description
Manufacturer
Atmel Corporation
Specifications of ATmega329PA
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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26.4.3
26.4.4
26.4.5
26.5
26.5.1
8284D–AVR–6/11
Boundary-scan Chain
SAMPLE_PRELOAD; 0x2
AVR_RESET; 0xC
BYPASS; 0xF
Scanning the Digital Port Pins
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
The active states are:
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as Data Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-scan chain is applied to the output latches. However, the
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as Data Register. Note that the reset will be active as long as there is
a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
• Capture-DR: Loads a logic “0” into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connection.
Figure 26-2 on page 265
function. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn –
function, and a bi-directional pin cell that combines the three signals Output Control – OCxn,
Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and
pin indexes are not used in the following description
The Boundary-scan logic is not included in the figures in the Data Sheet.
266
Boundary-scan details from
page
When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Reg-
ister value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output
output latches are not connected to the pins.
shows a simple digital port pin as described in the section
266.
shows the Boundary-scan Cell for a bi-directional port pin with pull-up
Figure 26-2 on page 265
replaces the dashed box in
”I/O-Ports” on page
Figure 26-3 on page
Figure 26-3 on
66. The
264
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