AT90PWM2B Atmel Corporation, AT90PWM2B Datasheet - Page 184

• Manufacturer Part Number: AT90PWM2B
• Manufacturer: Atmel Corporation

Specifications of AT90PWM2B

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18.3
184
Clock Generation
AT90PWM2/3/2B/3B
Figure 18-1. USART Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, Parity Generator and Control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
1. Refer to
pin placement.
Pin
Configurations3,
UCSRA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDR (Receive)
UDR (Transmit)
UBRR[H:L]
(1)
Table 11-9 on page
UCSRB
73, and
SYNC LOGIC
GENERATOR
RECOVERY
RECOVERY
CHECKER
PARITY
CLOCK
PARITY
DATA
CLKio
Table 11-7 on page 72
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
RX
TX
Receiver
UCSRC
4317J–AVR–08/10
for USART
XCK
TxD
RxD