AT90PWM2B Atmel Corporation, AT90PWM2B Datasheet - Page 180

• Manufacturer Part Number: AT90PWM2B
• Manufacturer: Atmel Corporation

Specifications of AT90PWM2B

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.2.5
17.2.6
180
AT90PWM2/3/2B/3B
SPI Status Register – SPSR
SPI Data Register – SPDR
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the clk
the following table:
Table 17-4.
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
or lower.
The SPI interface on the AT90PWM2/2B/3/3B is also used for program memory and EEPROM
downloading or uploading. See
verification.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
Relationship Between SCK and the Oscillator Frequency
SPD7
SPIF
R/W
X
R
7
7
0
Table
WCOL
SPD6
R/W
SPR1
R
6
X
6
0
0
0
1
1
0
0
1
1
17-4). This means that the minimum SCK period will be two CPU
Serial Programming Algorithm294
SPD5
R/W
5
X
R
5
–
0
SPD4
R/W
SPR0
4
X
R
4
–
0
0
1
0
1
0
1
0
1
SPD3
R/W
3
X
R
3
–
0
SCK Frequency
f
f
f
f
f
f
f
f
clkio
clkio
clkio
clkio
clkio
clkio
clkio
clkio
SPD2
R/W
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
2
X
R
2
–
0
IO
for serial programming and
frequency f
SPD1
R/W
X
1
R
1
–
0
SPD0
SPI2X
R/W
R/W
X
0
0
0
clkio
4317J–AVR–08/10
is shown in
Undefined
SPDR
SPSR
clkio
/4