AT90PWM2B Atmel Corporation, AT90PWM2B Datasheet - Page 134

• Manufacturer Part Number: AT90PWM2B
• Manufacturer: Atmel Corporation

Specifications of AT90PWM2B

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16.5
16.5.1
134
Functional Description
AT90PWM2/3/2B/3B
Waveform Cycles
The waveform generated by PSC can be described as a sequence of two waveforms.
The first waveform is relative to PSCOUTn0 output and part A of PSC. The part of this waveform
is sub-cycle A in the following figure.
The second waveform is relative to PSCOUTn1 output and part B of PSC. The part of this wave-
form is sub-cycle B in the following figure.
The complete waveform is ended with the end of sub-cycle B. It means at the end of waveform
B.
Figure 16-4. Cycle Presentation in 1, 2 & 4 Ramp Mode
Figure 16-5. Cycle Presentation in Centered Mode
Ramps illustrate the output of the PSC counter included in the waveform generators. Centered
Mode is like a one ramp mode which count down up and down.
Notice that the update of a new set of values is done regardless of ramp Mode at the top of the
last ramp.
4 Ramp Mode
2 Ramp Mode
1 Ramp Mode
Centered Mode
Ramp A0
Sub-Cycle A
Ramp A
Ramp A1
PSC Cycle
Ramp B0
Sub-Cycle B
Ramp B
Ramp B1
PSC Cycle
UPDATE
UPDATE
4317J–AVR–08/10