AT90PWM1 Atmel Corporation, AT90PWM1 Datasheet - Page 196

• Manufacturer Part Number: AT90PWM1
• Manufacturer: Atmel Corporation

Specifications of AT90PWM1

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

19.8.3
196
AT90PWM1
ADC Control and Status Register B– ADCSRB
• Bit 5 – ADATE: ADC Auto trigger Enable Bit
Set this bit to enable the auto triggering mode of the ADC.
Clear it to return in single conversion mode.
In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB register.
See
• Bit 4– ADIF: ADC Interrupt Flag
Set by hardware as soon as a conversion is complete and the Data register are updated with the
conversion result.
Cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF can be cleared by writing it to logical one.
• Bit 3– ADIE: ADC Interrupt Enable Bit
Set this bit to activate the ADC end of conversion interrupt.
Clear it to disable the ADC end of conversion interrupt.
• Bit 2, 1, 0– ADPS2, ADPS1, ADPS0: ADC Prescaler Selection Bits
These 3 bits determine the division factor between the system clock frequency and input clock of
the ADC.
The different setting are shown in
Table 64. ADC Prescaler Selection
Bit
Read/Write
Initial Value
• Bit 7 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to convert with
an ADC clock frequency higher than 200KHz.
• Bit 3, 2, 1, 0– ADTS3:ADTS0: ADC Auto Trigger Source Selection Bits
These bits are only necessary in case the ADC works in auto trigger mode. It means if ADATE
bit in ADCSRA register is set.
In accordance with the Table 19-1, these 3 bits select the interrupt event which will generate the
trigger of the start of conversion. The start of conversion will be generated by the rising edge of
the selected interrupt flag whether the interrupt is enabled or not. In case of trig on PSCnASY
ADPS2
0
0
0
0
1
1
1
1
Table 19-1 on page
ADPS1
0
0
1
1
0
0
1
1
ADHSM
7
0
-
197.
6
0
-
-
ADPS0
0
1
0
1
0
1
0
1
Table
5
0
-
-
64.
ADASCR
Division Factor
2
2
4
8
16
32
64
128
R/W
4
0
ADTS3
R/W
3
0
ADTS2
R/W
2
0
ADTS1
R/W
1
0
ADTS0
R/W
0
0
4378C–AVR–09/08
ADCSRB