AT90PWM1 Atmel Corporation, AT90PWM1 Datasheet - Page 140

• Manufacturer Part Number: AT90PWM1
• Manufacturer: Atmel Corporation

Specifications of AT90PWM1

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16.8.4
16.8.4.1
16.8.4.2
140
AT90PWM1
PSC Input Configuration
Filter Enable
Signal Polarity
Figure 16-19. Burst Generation
The PSC Input Configuration is done by programming bits in configuration registers.
If the “Filter Enable” bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal.
The disable of this function is mainly needed for prescaled PSC clock sources, where the noise
cancellation gives too high latency.
Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSC clock
to deactivate the outputs (emergency protection of external component). Likewise when used as
fault input, PSCn Input A or Input B have to go through PSC to act on PSCOUTn0/1/2/3 output.
This way needs that CLK
(PAOCnA/B), PSCnIN0/1 input can desactivate directly the PSC output. Notice that in this case,
input is still taken into account as usually by Input Module System as soon as CLK
PSC Input Filterring
One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit
description in Section “PSC n Input A Control Register – PFRCnA”, page 16116.25.13.
PSCOUTn0
PSCOUTn1
PSCn Input A
(high level)
PSCn Input A
(low level)
PSC Input
Module X
CLK
PSC
PSC
OFF
is running. So thanks to PSC Asynchronous Output Control bit
Digital
Filter
4 x CLK
PSC
BURST
Ouput
Stage
PSCn Input A or B
PSCOUTnX
PIN
PSC
4378C–AVR–09/08
is running.