AT89LP51ID2 Atmel Corporation, AT89LP51ID2 Datasheet - Page 91

• Manufacturer Part Number: AT89LP51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

14.1
Table 14-3.
Note:
3714A–MICRO–7/11
T2CON Address = 0C8H
Bit Addressable
Bit
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Timer 2 Registers
The Timer 2 operating mode depends on bits in both T2CON and T2MOD as shown in
bits have priority over CP/RL2.
TF2
Function
Timer 2 Overflow Flag
Set by hardware when Timer 2 overflows and must be cleared by software. TF2 will not be set when either
RCLK = 1 or TCLK = 1. TF2 will generate an interrupt when ET2 is set in IEN0.
Timer 2 External Flag
Set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is
enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2
does not cause an interrupt in up/down counter mode (DCEN = 1) or dual-slope mode.
Receive Clock Enable
Set to use Timer 2 overflow pulses for receive clock in serial port Modes 1 and 3. Clear to use Timer 1 overflows for the
receive clock.
Transmit Clock Enable
Set to use Timer 2 overflow pulses for transmit clock in serial port Modes 1 and 3. Clear to use Timer 1 overflows for the
transmit clock.
Timer 2 External Enable
When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to
clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
Timer 2 Run Control
Start/Stop control for Timer 2. TR2 = 1 starts the timer. TR2 = 0 stops the timer.
Timer/Counter Select 2
Clear C/T2 = 0 for timer function. Set C/T2 = 1 for external event counter on T2 (P1.0) (falling edge triggered). C/T2 must
be 0 to use clock out mode.
Capture/Reload Select
CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic
reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or
TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
7
T2CON – Timer/Counter 2 Control Register
EXF2
Control and status bits for Timer 2 are contained in registers T2CON (see
T2MOD (see
16-bit timer register for Timer 2. The register pair {RCAP2H, RCAP2L} at addresses 0CBH and
0CAH are the 16-bit Capture/Reload register for Timer 2 in capture and auto-reload modes.
6
RCLK
5
Table
14-4). The register pair {TH2, TL2} at addresses 0CDH and 0CCH are the
TCLK
4
AT89LP51RD2/ED2/ID2 Preliminary
EXEN2
3
TR2
2
Table
Reset Value = 0000 0000B
14-1. The RCLK, TCLK and T2OE
C/T2
1
CP/RL2
Table
0
14-3) and
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