AT89LP51ID2 Atmel Corporation, AT89LP51ID2 Datasheet - Page 53

• Manufacturer Part Number: AT89LP51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

7. Reset
7.1
3714A–MICRO–7/11
Power-on Reset
During reset, all I/O Registers are set to their initial values, the port pins are set to their default
m o d e , a n d t h e p r o g r a m s t a r t s e x e c u t i o n f r o m t h e R e s e t V e c t o r , 0 0 0 0 H . T h e
AT89LP51RD2/ED2/ID2 has six sources of reset: power-on reset, brown-out reset, external
reset, hardware watchdog reset, PCA watchdog reset and software reset.
Figure 7-1.
A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level V
is nominally 1.4V. The POR is activated whenever V
cuit can be used to trigger the start-up reset or to detect a major supply voltage failure. The POR
circuit ensures that the device is reset from power-on. A power-on sequence is shown in
7-2. When V
lasting t
how long the device is kept in POR after V
until after V
activated again, without any delay, when V
Reset (i.e. a cold reset) will set the POF flag in PCON. The internally generated reset can be
extended beyond the power-on period by holding the RST pin active longer than the time-out.
The start-up timer delay is user-configurable with the Start-up Time User Fuses and depends on
the clock source
after a Brown-out Reset or when waking up from Power-down during internally timed mode. The
start-up delay should be selected to provide enough settling time for V
source. The device operating environment (supply voltage, frequency, temperature, etc.) must
meet the minimum system requirements before the device exits reset and starts normal opera-
tion. The RST pin may be held active externally until these conditions are met.
While the POR is active a reset output pulse will be generated on the RST pin to reset the board-
level circuitry. The output pulse is either open-drain or open-source as shown in
order to properly propagate this pulse to the rest of the board in the case of an external capacitor
or power-supply supervisor circuit, a 1 kΩ resistor should be placed in series with any external
driving circuitry as shown in
POR
DD
is started. When the initialization sequence completes, the start-up timer determines
DD
reaches the Brown-out Detector (BOD) threshold voltage V
Reset Subsystem Diagram
reaches the Power-on Reset threshold voltage V
(Table
RST
Watchdog
Watchdog
Hardware
Software
7-1). The Start-Up Time fuses also control the length of the start-up time
Reset
POR
BOD
PCA
AT89LP51RD2/ED2/ID2 Preliminary
Figure
7-5. The POR output pulse cannot be disabled.
DD
DD
falls below the POR threshold level. A Power-on
rise. The start-up timer does not begin counting
DD
is below the detection level. The POR cir-
DISRTO
Internal Reset
POR
, an initialization sequence
DD
BOD
and the selected clock
. The POR signal is
Figure
7-4. In
Figure
POR
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